Layout Engineer (f/m/d)

About usWe see the semiconductor industry as a realm of possibility. We see opportunity. We see the profound impact that our graphene solutions will have in transforming the industry. We invite you to join us in driving change with our fundamentally human-centered approach, uniting bright minds around a shared vision. The vision is: Prove to everybody that you can make a fundamental change. Prove with your knowledge and skills how things can be done differently. Together, we can change the paradigm of how the world connectsAbout our technologyThe semiconductor industry’s growing demand for more powerful chips with higher bandwidth and lower power finds its solution in our technology. We connect chips to high-throughput, low-delay computing networks. The key lies in harnessing the physical properties of graphene to combine electronic computing with photonic communication, allowing countless chips to interact almost as if they were one. Our graphene photonic innovation increases computing power and efficiency to a new order of magnitudeIn short, we connect chips to create powerful and energy-efficient networks, overcoming connectivity limitations in the semiconductor industry. We deliver the graphene solution The RoleWe are looking for a Layout Engineer to join our design team and support the development of layouts for photonic integrated circuits. You will maintain our layout infrastructure, help translate new designs into fabrication-ready layouts, and contribute to the implementation of new design rules and verification flows.To join our team, you should be excited to:Maintain and further develop our layout libraries and workflows in Synopsys Support designers in generating layouts for new photonic devices and circuitsRun design rule checks (DRC) and layout-versus-schematic checks (LVS)Investigate and resolve DRC violations, off-grid errors, and other layout issuesImplement new design rules Assemble layouts Support the mask flow from device layout through to mask