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Remoto
Sr Account Technical Executive II
Cadence · Remoto Brasil · Flexible / Remote
Publicada em 11/08/2026
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Key ResponsibilitiesLead technical engagement for Digital IC/Custom IC / Analog / RF design flows, with a primary focus on Innovus and Virtuoso platforms along with signoff technologies Partner with customer design and CAD teams to optimize layout productivity, quality, and time-to-marketDrive adoption of advanced capabilities such as: Constraint-driven and automation-assisted layoutDevice-level and full-chip layout methodologiesAdvanced node layout challenges (FinFET, GAA)EM and IR-aware layout and parasitic extraction flowsChampion the integration of AI-driven design techniques, including: Agentic AI workflows to automate design exploration, layout optimization, and verification tasksAI-assisted decision-making for layout trade-offs including PPA, matching, and parasiticsTranslate customer pain points into actionable requirements for R&D and product engineeringProvide technical leadership in methodology definition, flow development, and best practicesInfluence competitive replacements and expand footprint of Cadence Custom IC solutionsSupport executive-level discussions by linking technical value such as PPA, productivity, and risk reduction to business outcomesKey Qualifications Digital IC Deep hands-on experience with digital design flow including Genus/Innovus , Quantus , Tempus and PegasusClear understanding of PPA tradeoff's and other key concerns for design teamsAbility to think full stack/flow - interconnect technologies and drive value propositionExperience working with design teams on large SOC tapeouts Understanding of foundry working model and care bouts - knowledge of PDK enablement , DTCO and technology entitlement a plus Custom IC and Virtuoso ExpertiseDeep hands-on experience with the Cadence Virtuoso Platform, including: Virtuoso Layout Suite (XL, GXL, EXL)Schematic-driven layout and LVS flowsDRC and physical verification integrationStr
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